1. Field of the Invention
This invention relates to a circuit for driving a magnetic head of a magnetic recording apparatus.
2. Description of the Related Art
A magnetic head driving circuit generally comprises two sets of transistor-pair for switching a magnetic head according to an input signal and a resistor element for absorbing a surge voltage. A conventional magnetic head driving circuit is shown in FIG. 1.
In the circuit diagram shown in FIG. 1, the collector of a first NPN transistor Q1 and the collector of a second NPN transistor Q2 are connected in common and respectively supplied with a power source voltage Vcc. The emitter of the first transistor Q1 is connected to the collector of a third NPN transistor Q3 and the emitter of the second transistor Q2 is connected to the collector of a fourth NPN transistor Q4. A magnetic head 3 is connected between a connecting point a of the first transistor Q1 and third transistor Q3 and a connecting point b of the second transistor Q2 and fourth transistor Q4. A surge voltage absorbing resistor 4 is connected parallel to the magnetic head 3. The emitter of the third transistor Q3 and that of the fourth transistor Q4 are connected in common to a constant current source 5. Thus, the magnetic head driving circuit structured as above makes an H bridge circuit.
The first transistor Q1 has its base supplied with a first input signal VIN1, the second transistor Q2 has its base supplied with a first inverted input signal VIN1, the third transistor Q3 has its base supplied with a second inverted input signal VIN2 and the fourth transistor Q4 has its base supplied with a second input signal VIN2. As shown in FIG. 1, the first input signal VIN1 may take a low (L) level voltage of 3.5 V or a high (H) level voltage of 4.5 V. On the other hand, the second input signal VIN2 may take an L-level voltage of 1 V or an H-level voltage of 2 V.
With the conventional magnetic head driving circuit as shown above, when the first input signal VIN1 and second input signal VIN2 respectively are of the H-level voltage both, the first transistor Q1 and fourth transistor Q4 switch ON and both the second transistor Q2 and third transistor Q3 switch OFF, so that the magnetic head 3 has an electric current flowing from the connecting point a to the connecting point b (in the right direction of FIG. 1). On the other hand, when the first and second input signals VIN1 and VIN2 respectively are of the L-level voltage both, the second and third transistors Q2 and Q3 switch ON and both the first and fourth transistors Q1 and Q4 switch OFF, so that the magnetic head 3 has an electric current flowing from the connecting point b to the connecting point a (in the left direction of FIG. 1).
When the electric current is in the magnetic head 3, that is, a magnetic head current is inverted it flows in the direction from the right to the left or from the left to the right. The input signals VIN1 and VIN2 are simultaneously switched from the H-level to the L-level or from the L-level to the H-level. At the moment when the magnetic head current is inverted, a surge voltage is generated from the magnetic head 3, but this surge voltage is restricted by the surge voltage absorbing resistor 4 provided in parallel to the magnetic head 3, resulting in the protection of the magnetic head 3 from the surge voltage.
For example, when a constant current IE flowing into the constant electric current source 5 is 30 mA and a resistance value of the surge absorbing resistor 4 is 500 .OMEGA., the voltage across the surge absorbing resistor 4 can be determined as follows; EQU 30 mA.times.500=1.5 V (1).
In addition, for example, when the magnetic head 3 has an inductance of 5 .mu.H, its time constant can be determined as follows; EQU 5 .mu.H/500 .OMEGA.=10 nsec (2).
As a result, the reverse bias voltage applied between the base and emitter of the first transistor Q1 has a peak value of about 1 V.
With the driving circuit shown above, considerations will be made below of a case such that at one moment of time, the first input signal VIN1 inputted to the base of the first transistor Q1 is of the H-level (4.5 V), the first inverted input signal VIN1 inputted to the base of the second transistor Q2 is of the L-level (3.5 V), the second inverted input signal VIN2 inputted to the base of the third transistor Q3 is of the L-level (1 V) and the second input signal VIN2 inputted to the base of the fourth transistor Q4 is of the H-level (2 V). At the next moment of time, both of the first and second input signals are simultaneously switched to the L-level. In this case, the magnetic head 3 has a current from the connecting point a toward the connecting point b, as already described above.
In this consideration, no problem arises insofar as the input signals VIN1 and VIN2 are completely and simultaneously switched to the L-level. However, for example, when the inversion of the first input signal VIN1 is delayed, even slightly, from that of the second input signal VIN2, the fourth transistor Q4 switches OFF and third transistor Q3 switches ON slightly before the first transistor Q1 switches OFF and second transistor Q2 becomes ON. As a result, the electric potential at the connecting point b will be increased. For example, the base voltage of the first transistor Q1 is 4.5 V, the voltage VBE between the base and emitter thereof is 0.7 V and the surge voltage at that time is 500 .OMEGA..times.300 mA=1.5 V, the electric potential at the connecting point b becomes 5.3 V momentarily, as follows; EQU 4.5 V-0.7 V+1.5 V=5.3 V (3).
At that time, however, the base voltage of the second transistor Q2 is still at the L-level, that is, at 3.5 V, so that the reverse bias voltage applied between the base and emitter of the second transistor Q2 can be increased to above 2 V as calculated below. EQU 5.3 V-3.5 V=1.8 V=2 V (4).
However, accompanied with a recent trend toward making high density and high speed integrated circuits, the withstand voltage of transistors has a tendency to be reduced. Referring to the reverse bias withstand voltage between the base and emitter, it is about 5 V conventionally, but, recently it has been reduced to about 1.5 V. Considered from this point of view, in the conventional magnetic head driving circuit shown above, if a time delay occurs in inverting the input signals VIN1 and VIN2, such a problem will arise because an electric property (for example, current amplification factor) is degraded.
In addition, even if an attempt is made to shorter the switching time of the magnetic head current by further increasing the resistance value of the surge absorbing resistor 4, it cannot be realized because there is no conservative reverse bias withstand voltage between the base and emitter of the second transistor Q2.
Thus, object of this invention is to provide a magnetic head driving circuit in which even if a time delay occurs in converting the input signals of transistors, these transistors can be protected from the reverse bias voltages, and the switching time of a current flowing into the magnetic head can be decreased.